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Tensilica Announces Major IC Design Automation Breakthrough, the Automatic Generation of Optimized Programmable RTL Engines From Standard C Code
Automates RTL Block Design; Adds Flexibility Through Programmability
SANTA CLARA, Calif.—(BUSINESS WIRE)—July 7, 2004—
Tensilica(R), Inc. today announced that it has achieved a major
design automation breakthrough -- the automated design of optimized
configurable processors from standard C code using the company's new
XPRES(TM) (Xtensa(R) PRocessor Extension Synthesis) compiler. This
tool enables the rapid development of optimized system-on-chip (SOC)
devices without requiring designers to hand code their hardware using
design languages like VHDL and Verilog, which take months of design
and verification effort. Instead, designers input the original
algorithm that they're trying to optimize, written in standard ANSI
C/C++, and the XPRES compiler, coupled with Tensilica's automated
processor generation technology, automatically generate an RTL
(register transfer level) hardware description and associated software
tool chain. In less than an hour, the resulting hardware block is
delivered in the form of a pre-verified Xtensa LX processor core,
enabling customers to future proof their designs due to its inherent
programmability, and avoid the cost and risk associated with verifying
custom logic. Additionally, the generated RTL fully rivals the
performance and efficiency of hand-coded RTL blocks with many
concurrent operations, efficient data types, and optimized multiple
wide deep pipelines.
Until now, most early approaches for IC design concentrated on
generating custom RTL hardware for tasks that could not be performed
by the processor due to performance constraints. In May, Tensilica
unveiled Xtensa LX with a new architecture that eliminates these
performance barriers and allows the processor to be used in place of
RTL. The use of processors not only reduces design time, complexity
and cost, but also helps future-proof products. Because processors are
inherently programmable, small changes due to standards updates or new
market requirements can be easily made in software rather than
hardware, eliminating the need to completely re-spin a chip. With
average chip design cost now exceeding $5 million, Tensilica's
technology has the potential to significantly change the ROI (return
on investment) in the semiconductor business.
"It's not just that XPRES can automatically generate custom
hardware from C/C++ code, a focus of widespread research and
development," stated Tom Halfhill, senior analyst for In-Stat/MDR
(www.mdronline.com). "Rather, it's the whole tool chain and design
flow that sets Tensilica's technology apart. Tensilica is closer than
any other company to realizing a vision of software-driven automated
hardware design that has mesmerized engineers, academic researchers,
and entrepreneurs for decades."
"Our XPRES Compiler is the next step in Tensilica's vision of an
automated IC-design and firmware-development process based on multiple
configurable processors instead of RTL blocks," added Chris Rowen,
Tensilica's President and CEO. "With XPRES, we can automatically
determine which functions should be accelerated in hardware and
generate a comprehensive hardware/software solution for those
functions. No RTL coding is required -- our XPRES compiler
automatically generates the necessary RTL code that is pre-verified to
be correct by construction."
Tensilica's XPRES compiler innovation is expected to drive a
transition in the industry similar to the transition in the late 1980s
from schematic capture to a synthesis driven methodology using the
Verilog or VHDL programming languages. By the early 1990s, it was
apparent that these languages produced equivalent or better results in
a fraction of the time it took to use schematic capture. Similarly,
today designers can replace RTL blocks designed with these languages
with configurable processors. The XPRES Compiler allows designers to
get high-performance results similar to hand-coding RTL, but in a much
shorter time period. As a result, Tensilica projects a fast transition
to its methodology -- using multiple configurable processors instead
of RTL blocks.
In 1999, Tensilica introduced the first configurable processor
generator with automated software, hardware, modeling and EDA support.
Changes can be made in the form of configuration options or
designer-defined TIE (Tensilica Instruction Execution) instructions.
Now, with the XPRES Compiler, designers no longer have to manually
select configuration options and write TIE (Tensilica Instruction
Extension) instructions to modify the processor design.
Preserves C Code Portability
Tensilica's XPRES Compiler can generate an optimized Xtensa LX
processor that is reusable over a range of similar application
software code. Similar code can take advantage of the acceleration
without any modification. This is a crucial difference between using
an Xtensa LX processor to speed an application and today's
co-processor acceleration method, which uses RTL design to create a
block of hard-wired logic that is not programmable and must
communicate with the processor across a narrow 32-bit bus. Because RTL
isn't programmable, it can't be used across related applications
without modifying the hardware and creating a new IC. If changes are
needed in hardware, the RTL has to be redesigned and a new IC must be
produced. However, with the XPRES Compiler, changes can easily be made
in software, preserving the initial hardware investment.
Using the XPRES Compiler
The XPRES Compiler gives the design team complete usage
flexibility. It can be used in full automation mode, where a C/C++
program is input and optimized TIE instructions are output, or it can
be used under full designer control, so the designer can guide the
tool, select instructions, and even tune the original application to
take better advantage of the added hardware instructions.
"We expect that many design teams will run their code through the
XPRES compiler, check the results, and find that their performance
goals have been met without any further optimization," stated Bernie
Rosenthal, Tensilica's Senior Vice President of Marketing and Sales.
"But we also have a large group of power users that will want to check
and tweak every optimization and possibly even re-code sections of the
original application to ensure that the fastest possible results are
achieved."
A simple 5-step process explains how the XPRES Compiler is used.
Step 1. Compile the original C/C++ application code. No recoding
is required. Tensilica's C/C++ compiler generates information about
the application, performing such functions as ranking code regions by
frequency, determining which loops can be vectorized, generating
dataflow graphs for important regions, and performing operation counts
for each type of opcode for every region.
Step 2. Run the XPRES Compiler to determine the best processor
configuration and extensions for that code. The XPRES Compiler
evaluates all generated configurations across all regions and
determines the best set of merged configurations given a particular
gate-count budget. The XPRES Compiler is able to conduct abstract
evaluations and search through millions of configuration
possibilities, usually in less than an hour.
Step 3. (Optional) Manually tune the automatically generated
custom configuration. Power users will want to refine or optimize the
code and add additional instructions for algorithms or functions that
other programs might need.
Step 4. Generate the optimized processor. Use Tensilica's proven
processor-generator technology and, in less than one hour, generate
the complete processor RTL with EDA support, complete
software-development tool chain, simulations and modeling environment,
and RTOS support.
Step 5. Compile and use the original, unmodified C/C++ application
using the newly optimized processor configuration. No need to modify
the C code to make it Tensilica-specific. No need to use
time-consuming assembly level optimizations. No need to design custom
hardware accelerators using traditional RTL design methods.
Pricing and Availability
Pricing starts at $100,000 per year for a floating license. The
XPRES Compiler will be available in the third quarter of 2004. The
XPRES Compiler license requires a license for the Xtensa LX processor.
About Tensilica
Tensilica was founded in July 1997 to address the growing need for
optimized, application-specific microprocessors for high-volume
embedded applications. With the Xtensa and Xtensa LX configurable and
extensible microprocessor cores, Tensilica is the only company that
has automated and patented the time-consuming process of generating a
customized microprocessor core along with a complete
software-development tool environment, producing new configurations in
a matter of hours. These customized processors rival hand-coded RTL in
performance and add a needed level of programmability. For more
information, visit www.tensilica.com.
Editors' Notes:
-- Tensilica, Xtensa and Xtensions Network are registered
trademarks belonging to Tensilica Inc.
-- Tensilica's announced licensees include Agilent, ALPS, AMCC
(JNI Corporation), Astute Networks, Avision, Bay Microsystems,
Berkeley Wireless Research Center, Broadcom, Cisco Systems,
Conexant Systems, Cypress, Crimson Microsystems, ETRI,
FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes
Network Systems, Ikanos Communications, LG Electronics,
Marvell, MediaWorks, NEC Laboratories America, NEC
Corporation, Nippon Telephone and Telegraph (NTT), Olympus
Optical Co. Ltd., S2io, Solid State Systems, Sony,
STMicroelectronics, Stretch Inc., TranSwitch Corporation, and
Victor Company of Japan (JVC).
Contact:
Tensilica, Inc.
Paula Jones, 408-327-7343
paula@tensilica.com
or
Joany Draeger, 650-365-3395
joany@taniscomm.com
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